1. Field of the Invention
The present invention generally relates to a nonvolatile ferroelectric memory device having a hierarchical bit line architecture, and more specifically, to a nonvolatile ferroelectric memory device comprising a single large page cell array block including the whole unit cells and a high capacity wide page buffer corresponding to all main bit lines in the page cell array block, thereby improving the efficiency of the memory cell and the data processing speed.
2. Description of the Prior Art
Generally, a ferroelectric random access memory (hereinafter, referred to as ‘FeRAM’) has a data processing speed as fast as a Dynamic Random Access Memory DRAM and conserves data even after the power is turned off.
The FeRAM having structures similar to the DRAM includes the capacitors made of a ferroelectric substance, so that it utilizes the characteristic of a high residual polarization of the ferroelectric substance in which data is not deleted even after an electric field is eliminated.
The technical contents on the above FeRAM are disclosed in the Korean Patent Application No. 1998-14400 by the same inventor of the present invention. Therefore, the basic structure and the operation on the FeRAM are not described herein.
FIG. 1 is a diagram illustrating a conventional nonvolatile ferroelectric memory device.
The nonvolatile ferroelectric memory device of FIG. 1 comprises a plurality of cell array blocks 10 comprising a plurality of cell arrays, a common data bus 20 shared in the plurality of cell array blocks 10 and for transmitting data, and a sense amplifier unit 30 for sensing and buffering data applied through the common data bus 20. Here, a word line driving unit W/L and a plate line driving unit P/L are included in each cell array block 10. Each cell array block 10 is selectively connected to the common data bus 20 in response to a column selecting signal, and reads or writes data.
In the nonvolatile ferroelectric memory device of FIG. 1, since the column selecting signal is selectively activated in each cell array block 10, only data of the corresponding cell array block 10 are applied to the common data bus 20.
In the above-described nonvolatile ferroelectric memory device of FIG. 1, since the word line driving unit W/L and the plate line driving unit P/L are included in each cell array block 10, these driving units occupy a large area in the memory device. In addition, since it is necessary to access the cell array block 10 in every read or write operation, the processing of a great deal of data requires much access time. Furthermore, attention has been more directed to the problem of the access time as memory capacity becomes larger.